CDR — clock and data recovery

A serial optical link carries no separate clock: the receiver must recover the clock from the data stream itself and then re-sample ("retime") the bits against it. The circuit that does this is the CDR (clock and data recovery). Where the CDR sits — in the host or inside the module — is one of the defining differences between form factors, and its control bits are part of the memory CodingBox reads and codes.

What a CDR does

1. Extracts the clock from the incoming bit transitions with a phase-locked loop.
2. Retimes the data — re-samples each bit at the recovered clock edge, so timing noise (jitter) accumulated on the way is removed.
3. Regenerates clean edges towards the next stage (laser driver on the Tx side, host SerDes on the Rx side).

A CDR therefore acts as a jitter reset point. Every link has a jitter budget shared between the host PCB trace, the connector and the module; a retimer in the module lets the host side spend its share loosely.

Host-side or module-side

This is exactly why SFP+ beat XFP for dense 10G switching, and why 100G modules run hotter than 40G ones.

Where it lives in module memory

SFF-8636 (QSFP+/QSFP28) — see SFF-8636:

CMIS (QSFP-DD, OSFP, QSFP112) — Page 01h advertises Tx/Rx CDR support and whether bypass is controllable; Page 10h holds the per-lane Tx/Rx CDR enable (bypass) controls, and the data-path state machine will not reach activated if a required CDR cannot lock (CMIS issues).

SFF-8472 (SFP/SFP+/SFP28) — no standard CDR control; the module's CDR (if any) is managed internally. The related host-visible mechanism is rate select, which switches receiver bandwidth between rate groups.

Why it matters in practice

• Multi-rate modules. A CDR locks to a rate range. A 25G module used at 10G, or a 100G QSFP28 broken out to 4×10G, must have a CDR that supports the lower rate — or the host must bypass it (byte 98 / CMIS). "Works at 25G, dead at 10G" is usually this.
• Loss of lock as a diagnostic. LOL flags mean the CDR cannot recover a clock: signal too degraded, wrong rate, or no signal — check Rx power and rate settings before suspecting the module (DDM levels).
• Power and latency. Each retimer costs power (tens to hundreds of mW at 25G; watts for PAM4 DSPs) and adds latency. Short DAC links and latency-sensitive fabrics often run with CDR bypassed.
• Coding consistency. When recoding a QSFP28, the CDR-present bits (byte 129) must match the hardware: a host that believes CDRs are present may leave them enabled at a rate the missing/different CDR cannot handle. See QSFP family hardware specs.

In CodingBox

The EEPROM editor names these fields on hover — CDR present, CDR control, LOL flags, Options — per SFF-8636 or CMIS, so you can read a module's CDR configuration, see whether a lane has lost lock, and keep the CDR bits consistent with the hardware when coding identity.

"Links at 25G, dead at 10G" and other rate-lock symptoms are worked through in Speed, rate & mode problems.

Where the CDR sits among driver, TIA and controller, and how PAM4 modules absorb it into a DSP with equalisation and gearboxing: Module electronics, Modulation & DSP.

Which host interfaces expect a retimed module (XFI, CAUI-4 C2M, PAM4 AUIs) and which tolerate a linear one (SFI, LPO): XGMII, XAUI and the AUI family.