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Bahasa Melayu OSFP-XD
Đội ngũ của chúng tôi đang thực hiện bản dịch. Bài viết này tạm thời chưa có bản tiếng Việt và đang được hiển thị bằng tiếng Anh.
OSFP-XD (Octal Small Form-factor Pluggable, eXtra Density) doubles the electrical lanes of OSFP from eight to sixteen while keeping the OSFP faceplate footprint. With 100G lanes that gives 1.6 Tb/s per module today; with 200G lanes, 3.2 Tb/s. It was created by a group of switch, silicon and optics vendors (the OSFP-XD MSA, formed in 2022) as the density path for 51.2T and 102.4T switch generations and for AI fabrics — the alternative to OSFP224, which reaches 1.6T by speeding up eight lanes instead. The base form factor is described in OSFP.
Key facts
| Lanes × rate | 16 × 100G (106.25 GBd PAM4) → 1.6T; 16 × 200G (212.5 GBd) → 3.2T |
| Total | 1.6T (first generation), 3.2T (next) |
| Electrical interface | 16-lane host interface at 100G/lane (1.6T as 2 × 800GAUI-8 or 1.6TAUI-16 class); later 200G/lane |
| Optical PMDs | 1.6T DR8 (8 × 200G λ), 2 × 800G DR4 / 2 × 800G 2×FR4 (twin-port), 1.6T 2×FR4, MMF SR16/VR16 variants; 3.2T optics to follow |
| Connectors | 2 × MPO-12 APC / MPO-16 APC, 2 × LC duplex, 1.6T DAC/AEC |
| Power | higher envelope than OSFP — the class of tens of watts (roughly up to 40 W in the MSA envelope); integrated heat sink, same height and width as OSFP |
| Management | CMIS 5.x, identifier 21h (OSFP-XD with CMIS); 16 lanes across banks 0–1 |
| Where | 1.6T ports on 51.2T/102.4T switches (32 ports of 1.6T in 1RU), InfiniBand XDR twin-port, AI back-end fabrics |
Why sixteen lanes
| Path to 1.6T | Lanes | Lane rate | Needs |
|---|---|---|---|
| OSFP-XD | 16 | 100G | host ASIC with 100G/lane SerDes (available now); a denser connector and more heat |
| OSFP224 | 8 | 200G | host ASIC with 200G/lane SerDes; tighter channels but half the pins |
OSFP-XD lets a 1.6T port be built on today's 100G SerDes, which is why it appeared first on high-radix switch faceplates: a 51.2T ASIC exposes 512 lanes of 100G, and 32 OSFP-XD cages absorb them in a single rack unit. When 200G SerDes become mainstream the same cage carries 3.2T per module.
Mechanical and thermal
- Same faceplate density as OSFP — 32 (or 36) modules per 1RU; the module is the same width and height, marginally longer to accommodate the second row of contacts.
- Connector — twice the signal contacts of OSFP in a dual-row arrangement on the paddle card, qualified for 100G/lane at introduction and designed toward 200G/lane.
- Backward compatible cage — an OSFP-XD port accepts standard OSFP (8-lane) modules, which use the outer contact row and run at 400G/800G.
- Integrated heat sink as on OSFP, with the same finned (switch) vs riding-heat-sink (NIC) split; the higher power of 16-lane DSP optics makes airflow the limiting factor (Power & thermal).
Specifications
- OSFP-XD MSA hardware specification — mechanical, electrical, thermal; first released 2022, revised since.
- Optical PMDs from IEEE 802.3dj (200G/λ: 1.6TBASE-DR8, 800GBASE-DR4) and MSAs for 2×FR4 and MMF variants (Ethernet generations, Optical interface MSAs).
- Management: CMIS with identifier 21h registered in SFF-8024.
Management interface
CMIS with two banks: lanes 1–8 in bank 0 and 9–16 in bank 1 (lower byte 126 selects the bank for pages 10h–3Fh). Application descriptors describe 16-host-lane applications (one 1.6T data path) and their breakouts (2 × 800G, 4 × 400G, 8 × 200G); ConfigStatus and data-path states are read per bank (CMIS lane pages map). The power class byte and MaxPower reflect the larger envelope.
Compatibility notes
- OSFP-XD modules do not fit OSFP or QSFP-DD ports; OSFP-XD ports accept OSFP modules.
- Twin-port XD modules present two 800G ports; split cables 1:2 and 1:4 follow the InfiniBand NDR/XDR conventions (IB cabling).
- Sixteen lanes double the number of things that can degrade per port; per-lane pre-FEC BER and Rx monitoring across both banks is the operational baseline (VDM & FEC metrics, Link reliability).
- Passive DAC at 1.6T is limited to well under a metre; AEC and optics dominate even inside a rack (Cabling an AI cluster).
In CodingBox
CodingBox reads OSFP-XD with the CMIS decoder across both banks: identifier 21h, power class, application descriptors, module and data-path states and per-lane DDM for all sixteen lanes on Check transceiver, EEPROM editor and DDM. A cradle with an OSFP-XD cage and a power supply rated for the module's class is required (Programmers).