XGMII, XAUI, XFI/SFI and the AUI family: 10G to 800G

Tim kami sedang mengerjakan terjemahannya. Artikel ini untuk sementara belum tersedia dalam bahasa Indonesia dan ditampilkan dalam bahasa Inggris.

From 10 Gigabit onward the interface between host and module is a bundle of serial lanes, and its name tells you the rate, the lane count and the modulation: SFI is one 10G NRZ lane, CAUI-4 four 25G lanes, 400GAUI-8 eight 50G PAM4 lanes, 800GAUI-8 eight 100G PAM4 lanes. The module must accept exactly that bundle, retime or amplify it, and map it onto its optical lanes — which may be a different number. This page lists the interfaces, the chip-to-chip vs chip-to-module distinction with its compliance points, the OIF CEI specifications behind them, the electrical-to-optical lane mapping, and who does the signal conditioning on each generation.

10 Gigabit

Interface	Form	Where	Notes
XGMII (Cl. 46)	32-bit data + 4-bit control each way, DDR at 156.25 MHz, 74 signals	on-chip between MAC and PCS	≤ 7 cm; not on boards today
XAUI (Cl. 47)	4 lanes × 3.125 GBd, 8b/10b	MAC/XGXS ↔ PHY; XENPAK, X2, XPAK modules	up to 50 cm PCB; obsolete for modules
RXAUI	2 × 6.25 GBd	ASIC ↔ PHY (Marvell)	pin-saving XAUI
XFI (XFP MSA)	1 × 10.3125 GBd, 64b/66b	host ↔ XFP	module contains CDR — a retimed interface (XFP)
SFI (SFF-8431)	1 × 10.3125 GBd, 64b/66b	host ↔ SFP+	module usually limiting or linear without CDR; host SerDes does equalisation; compliance points B (host output), C (module output), D at the host input (SFP+)
10GBASE-KR (Cl. 72)	1 × 10.3125 GBd with link training	backplane; ASIC ↔ 10GBASE-T PHY	AN Clause 73
USXGMII	1 × 10.3125 GBd, rate-adapted	ASIC ↔ multigig PHY	SGMII & serial gigabit

SFI's "linear" option carried 10GBASE-LRM: the module passes the distorted multi-mode signal linearly and the host's electronic dispersion compensation (EDC) cleans it — the ancestor of today's LPO idea.

25, 40, 50 Gigabit

Interface	Lanes	Standard	Cage
25GAUI	1 × 25.78125 GBd NRZ	Annex 109A (C2C), 109B (C2M)	SFP28
XLAUI	4 × 10.3125 GBd	Annex 83A/B	QSFP+ (40GBASE-LR4 etc.)
XLPPI	4 × 10.3125, non-retimed parallel physical interface	Annex 86A	QSFP+ SR4/CR4 without CDR
50GAUI-2	2 × 26.5625 GBd NRZ	Annex 135B/C	QSFP28 (2 × 50G breakout), SFP56 (some)
50GAUI-1	1 × 26.5625 GBd PAM4	Annex 135D/E	SFP56, 50GBASE-SR/FR/LR modules

100 Gigabit

Interface	Lanes	Standard	Cage
CAUI-10	10 × 10.3125 GBd	Annex 83A/B	CFP, CXP, 100GBASE-SR10
CAUI-4	4 × 25.78125 GBd NRZ	Annex 83D (C2C), 83E (C2M)	QSFP28, CFP2/CFP4
CPPI-4	4 × 25.78, non-retimed	Annex 86A-style for SR4	QSFP28 SR4 without CDR (rare)
100GAUI-4	4 × 26.5625 GBd NRZ (with RS-FEC(544) framing)	Annex 135D/E	QSFP28 in 100GBASE-CR4/KR4 KP4 mode
100GAUI-2	2 × 53.125 GBd PAM4	Annex 135F/135G (C2M)	QSFP56 100G lanes, 2 × 100G breakout, DR/FR1 modules with 2-lane hosts
100GAUI-1	1 × 106.25 GBd PAM4	Annex 120F/120G (C2M) (802.3ck)	QSFP112, OSFP 100G-per-lane, SFP112

200, 400, 800 Gigabit

Interface	Lanes	Standard	Cage
200GAUI-8	8 × 26.5625 GBd PAM4	Annex 120B/C	QSFP-DD in 200G mode (rare)
200GAUI-4	4 × 53.125 GBd PAM4	Annex 120D/120E (C2M)	QSFP56, OSFP/QSFP-DD 2 × 200G
200GAUI-2	2 × 106.25 GBd PAM4	Annex 120F/G	QSFP112 2 × 200G, OSFP
400GAUI-16 (CDAUI-16)	16 × 26.5625 GBd NRZ	Annex 120B/C	CFP8
400GAUI-8 (CDAUI-8)	8 × 53.125 GBd PAM4	Annex 120D/120E (C2M)	QSFP-DD, OSFP (400G)
400GAUI-4	4 × 106.25 GBd PAM4	Annex 120F/120G (C2M)	QSFP112, OSFP 400G, half of an 800G port
800GAUI-8	8 × 106.25 GBd PAM4	802.3df annexes (C2C/C2M)	OSFP, QSFP-DD800
800GAUI-4 / 1.6TAUI-8	4 / 8 × 212.5 GBd PAM4	802.3dj (in progress)	OSFP224, OSFP-XD, QSFP-DD1600

C2C vs C2M and compliance points

	Chip-to-chip (C2C)	Chip-to-module (C2M)
Path	ASIC ↔ ASIC/PHY on the same board or across a connector	ASIC → host PCB → cage connector → module PCB → module IC
Reach	up to ~25–50 cm (NRZ), less at PAM4	~10–15 cm host trace + connector
Test points	TP0/TP5 at chip pins	TP1 (host output at module connector), TP1a (after a reference channel = module input), TP4 (module output at connector), TP4a (at host input after host channel)
Module role	—	must meet output spec at TP4 (eye, jitter, TDECQ-like metrics) and tolerate host signal at TP1a with the specified stressed eye
Retiming	both chips retime	module retimes (CDR/DSP) — or is linear (LPO) and relies on the host

Host boards are qualified against the C2M reference channel; a long or lossy host trace (high-radix 800G switches) is why retimers and gearboxes appear on switch boards (Inside a switch).

OIF CEI behind the IEEE annexes

OIF CEI	Rate / modulation	IEEE equivalent	Reach class
CEI-28G-VSR	28 GBd NRZ	CAUI-4 C2M	very short reach (module)
CEI-28G-SR / -MR / -LR	28 GBd NRZ	CAUI-4 C2C / backplane	short / medium / long (backplane)
CEI-56G-VSR-PAM4	56 GBd PAM4	400GAUI-8 / 200GAUI-4 C2M	module
CEI-56G-MR/LR-PAM4	56 GBd PAM4	200GBASE-KR4 class	backplane
CEI-112G-VSR-PAM4	112 GBd PAM4	400GAUI-4 / 800GAUI-8 C2M	module
CEI-112G-XSR / -MR / -LR	112 GBd PAM4	die-to-die / C2C / backplane	—
CEI-112G-Linear-PAM4	112 GBd PAM4	LPO host interface	module, linear
CEI-224G (in progress)	224 GBd PAM4	800GAUI-4 / 1.6TAUI-8	—

OIF publishes the electrical envelopes; IEEE annexes reference or align with them.

Electrical lanes vs optical lanes

Module	Electrical (host)	Optical (line)	Conversion in module
10GBASE-LR SFP+	1 × 10G	1 λ × 10G	none
40GBASE-LR4	4 × 10G	4 λ × 10G	none (WDM mux)
100GBASE-SR4 / LR4	4 × 25G NRZ	4 fibres / 4 λ × 25G	none
100GBASE-DR / FR1 / LR1	4 × 25G NRZ	1 λ × 100G PAM4	gearbox + PAM4 DSP (4:1)
100G on QSFP112 (100GAUI-1)	1 × 100G PAM4	1 × 100G PAM4	retime only
200GBASE-FR4	4 × 50G PAM4	4 λ × 50G PAM4	retime
400GBASE-DR4 / FR4	8 × 50G PAM4	4 fibres / 4 λ × 100G PAM4	gearbox 2:1 in DSP
400GBASE-SR8	8 × 50G PAM4	8 fibres × 50G PAM4	retime
400G on 400GAUI-4 hosts	4 × 100G PAM4	4 × 100G PAM4	retime (or LPO linear)
800G-DR8 / 2×FR4	8 × 100G PAM4	8 fibres / 2 × 4 λ × 100G	retime
800G-DR4 (200G/λ)	8 × 100G PAM4	4 × 200G PAM4	gearbox 2:1
1.6T-DR8 (OSFP224)	8 × 200G PAM4	8 × 200G PAM4	retime

The gearbox is why a 400G-DR4 module draws 8–10 W and a 400G-SR8 less, and why CMIS lists separate host and media interface IDs per application (CMIS).

Who conditions the signal

Generation	In the module	On the host
10G SFP+ (SFI)	limiting amp or linear TIA; no CDR on most	SerDes with CTLE/DFE equalisation; EDC for LRM
10G XFP (XFI)	CDR	plain SerDes
25G SFP28, 100G QSFP28	CDR on Tx and Rx (bypassable: SFF-8636 bytes 98/99)	SerDes FFE/DFE; pre-emphasis programmable in the module's control bytes (SFF-8636 page 03h 234–241: Rx output amplitude/emphasis, Tx input equalisation)
PAM4 200G–800G	DSP retimer with FFE/DFE/MLSE; host-side equaliser settings via CMIS (page 10h/11h Tx input EQ, Rx output amplitude/pre-cursor/post-cursor)	SerDes DSP
LPO 400G/800G	linear driver and TIA, no DSP	the switch ASIC's SerDes DSP compensates the whole channel; host must be LPO-capable and directly attached (DSP & LPO)
Retimed vs linear AEC/ACC cables	AEC: DSP in the plug; ACC: linear amplifier	as above (Cable internals)

Rate selection and CDR bypass controls: Rate & application selection, CDR.

In CodingBox

For SFF-8636 modules CodingBox shows the CDR-present bits, rate-select capability and the equalisation/emphasis control bytes; for CMIS modules the application table with host interface IDs (CAUI-4, 400GAUI-8, 100GAUI-1…) against media interface IDs — the declaration a host uses to pick lane count and modulation. A module advertising only 400GAUI-8 will not run on a 400GAUI-4 (QSFP112-class) port, however good its optics (Check transceiver, CMIS upper pages).

Jika Anda menemukan ketidakakuratan atau kesalahan dalam artikel ini, pilih bagian teks yang bersangkutan lalu tekan Ctrl+Enter untuk .