MII, RMII, GMII, RGMII: parallel interfaces to the PHY

The parallel media-independent interfaces connect a MAC to a copper PHY chip over a handful of centimetres of PCB — inside routers, small switches, access points, industrial controllers and every embedded board with an RJ45. They never reach a transceiver cage, but they are the reference point for everything that does: SGMII is "GMII serialised", XGMII is "GMII at 10G", and the PHY inside a copper SFP speaks one of them internally. This page gives pins, clocks and timing for MII, RMII, GMII and RGMII, the RGMII delay problem, in-band status, MDIO management, and the faults each interface produces.

MII (IEEE 802.3 Clause 22)

Item	Value
Rates	10 and 100 Mb/s
Data	4-bit TXD[3:0], 4-bit RXD[3:0]
Clocks	TX_CLK and RX_CLK from the PHY: 25 MHz (100M), 2.5 MHz (10M)
Control	TX_EN, TX_ER, RX_DV, RX_ER, CRS (carrier sense), COL (collision)
Management	MDC, MDIO (shared)
Signal count	16 data/control + 2 management
Levels	5 V / 3.3 V TTL
Reach	a few cm; one PHY per MAC

Still found on microcontrollers and FPGAs; superseded by RMII for pin count.

RMII (RMII Consortium spec v1.2)

Item	Value
Rates	10 and 100 Mb/s
Data	2-bit TXD[1:0], RXD[1:0]
Clock	single REF_CLK 50 MHz, shared by MAC and PHY; sourced by an oscillator, the MAC, or the PHY (PHY-clock-out mode)
Control	TX_EN, CRS_DV (carrier sense + data valid multiplexed), RX_ER (optional)
Signal count	7–9
10 Mb/s mode	each nibble repeated 10× at 50 MHz
Reach	cm

The 50 MHz reference-clock topology is the classic RMII bug: a PHY expecting an external clock while the SoC expects the PHY to drive it gives a dead interface with a healthy link LED.

GMII (Clause 35)

Item	Value
Rates	1000 Mb/s; falls back to MII signalling for 10/100
Data	8-bit TXD[7:0], RXD[7:0]
Clocks	GTX_CLK 125 MHz from the MAC for transmit; RX_CLK 125 MHz from the PHY for receive; TX_CLK from PHY used only in 10/100 fallback
Control	TX_EN, TX_ER, RX_DV, RX_ER, CRS, COL
Signal count	24 + management
Levels	2.5 V (3.3 V tolerant on many)
Reach	cm; timing budget tight at 125 MHz single-data-rate

Mostly an on-chip or FPGA interface today; RGMII took its place on boards.

RGMII (Reduced GMII, HP/Marvell specification v1.3 and v2.0)

Item	Value
Rates	10/100/1000
Data	4-bit TXD[3:0] and RXD[3:0] double data rate: low nibble on rising edge, high nibble on falling edge
Clocks	TXC 125 MHz (from MAC), RXC 125 MHz (from PHY); 25 / 2.5 MHz for 100M / 10M
Control	TX_CTL (TX_EN on rising edge, TX_EN xor TX_ER on falling), RX_CTL (RX_DV / RX_DV xor RX_ER)
Signal count	12
Levels	2.5 V (v1.3), 1.5 V HSTL or 1.8 V (v2.0 option); 3.3 V on some PHYs
Reach	≤ 10–15 cm matched-length traces

The delay problem

RGMII requires the clock to arrive 1.5–2.0 ns after the data edges at the receiver (setup/hold window). Three ways to get it:

Mode	Who adds the delay	Device-tree `phy-mode`	Notes
PCB delay (v1.3)	~5 cm of extra clock trace	`rgmii`	classic, fragile
Internal delay in PHY (RGMII-ID, v2.0)	PHY adds 2 ns on TX and RX clocks	`rgmii-id`	most common today
Internal delay in MAC/SoC	SoC adds it	`rgmii` with MAC-side delay register	—
Mixed	PHY on one direction only	`rgmii-txid`, `rgmii-rxid`	when only one side supports it

Adding the delay twice (PCB and PHY) or not at all produces the signature RGMII fault: link up at 1G with CRC errors or no traffic, while 100M works (100M has a 40 ns period and tolerates the skew). Fix by changing the PHY's delay register or the phy-mode.

In-band status

When idle, the PHY drives link, speed and duplex on RXD[3:0] so the MAC can reconfigure its clock divider without an MDIO read: RXD[0] link, RXD[2:1] speed (00 = 10, 01 = 100, 10 = 1000), RXD[3] duplex. Some MACs ignore it and rely on MDIO polling; mismatched expectations give a link that is up on the PHY and down on the MAC.

TBI and RTBI

Ten-Bit Interface: the 8b/10b-coded 1000BASE-X symbols (10 bits at 125 MHz, RTBI at DDR with 5 bits) between a MAC/PCS and an external SerDes or optical PHY. Obsolete on boards; its serial descendant is 1000BASE-X/SGMII (SGMII & serial gigabit).

Comparison

Interface	Pins (data + ctrl)	Clock	Max rate	Voltage	Typical use
MII	16	25 MHz from PHY	100M	3.3/5 V	MCUs, legacy
RMII	7–9	50 MHz shared	100M	3.3 V	embedded SoC + PHY
SMII	2–3/port	125 MHz	100M	3.3 V	multi-port PHYs (Cisco)
GMII	24	125 MHz (MAC tx / PHY rx)	1G	2.5 V	FPGA, on-chip
RGMII	12	125 MHz DDR	1G	2.5/1.8/1.5 V	SoC ↔ PHY on boards
SGMII	4 (2 pairs)	1.25 GBd embedded	1G (10/100 by replication)	CML	SoC ↔ PHY, SFP cages

PHY management: MDIO/MDC

Item	Clause 22	Clause 45
Addressing	5-bit PHY address, 5-bit register (32 registers)	5-bit port, 5-bit device (PMA/PMD, PCS, PHY XS, DTE XS, AN, vendor), 16-bit register
Key registers	0 control (reset, speed, AN enable, loopback), 1 status (link, AN complete), 2–3 PHY ID (OUI + model), 4 AN advertisement, 5 link-partner ability, 9/10 1000BASE-T control/status, 17+ vendor (RGMII delay, LEDs)	1.x PMA, 3.x PCS, 7.x AN, 30.x/31.x vendor
Speed	MDC ≤ 2.5 MHz (often faster in practice)	same
Linux tools	`mii-tool -v eth0`, `phytool read eth0/1/0`, `ethtool eth0`; driver via `phylib`, `phylink`	`phytool read eth0/1:1/0`

Contrast with pluggable modules, which are managed over I²C, not MDIO (Two-wire interface). A copper SFP's internal PHY is the exception: its MDIO registers are reachable through the module's I²C at a secondary address on many designs, which is how vendors set 10/100 fallback and auto-negotiation behaviour.

Common PHYs and their interfaces

PHY family	Interfaces	Typical board
Marvell 88E1111 / 88E1512 / 88E1510	GMII, RGMII, SGMII, TBI	routers, copper SFP modules (88E1111)
Realtek RTL8211F / RTL8201	RGMII / RMII	SBCs, consumer routers
Microchip KSZ9031 / KSZ8081 / LAN8720	RGMII / RMII / RMII	industrial, MCU boards
TI DP83867 / DP83848	RGMII, SGMII / MII, RMII	industrial
Broadcom BCM54xxx	RGMII, SGMII, QSGMII	enterprise switches (quad/octal PHYs)
Marvell 88E1543 / 88E1548	QSGMII quad	48-port access switches

Faults by interface

Symptom	Interface	Cause
No link ever, PHY ID reads fine	RMII	REF_CLK direction/source mismatch
100M works, 1G no traffic / CRC	RGMII	delay mode (ID) wrong or doubled
Link up on PHY LED, MAC says down	RGMII/SGMII	in-band status disabled on one side, or MDIO polling absent
Half the packets lost at 1G	GMII/RGMII	trace length skew, wrong voltage level
PHY not found on MDIO	any	wrong PHY address (strapping pins), MDIO pull-up missing
Speed stuck at 10/100	any	AN advertisement register limited, cable, or `phy-mode` without 1G support

In CodingBox

Nothing on this page runs through the module's EEPROM — except the copper SFP, whose internal PHY (typically an 88E1111-class part) sits behind the same I²C that CodingBox reads. When a copper module works at 1G but not at 10/100, the answer lies in that PHY's configuration and the host's SGMII/1000BASE-X mode, not in the A0h identity bytes (Copper Ethernet & DAC, SGMII & serial gigabit).