MII، RMII، GMII، RGMII: PHY کے ساتھ متوازی انٹرفیسز

The parallel media-independent interfaces connect a MAC to a copper PHY chip over a handful of centimetres of PCB — inside routers, small switches, access points, industrial controllers and every embedded board with an RJ45. They never reach a transceiver cage, but they are the reference point for everything that does: SGMII is "GMII serialised", XGMII is "GMII at 10G", and the PHY inside a copper SFP speaks one of them internally. This page gives pins, clocks and timing for MII, RMII, GMII and RGMII, the RGMII delay problem, in-band status, MDIO management, and the faults each interface produces.

MII (IEEE 802.3 Clause 22)

Still found on microcontrollers and FPGAs; superseded by RMII for pin count.

RMII (RMII Consortium spec v1.2)

The 50 MHz reference-clock topology is the classic RMII bug: a PHY expecting an external clock while the SoC expects the PHY to drive it gives a dead interface with a healthy link LED.

GMII (Clause 35)

Mostly an on-chip or FPGA interface today; RGMII took its place on boards.

RGMII (Reduced GMII, HP/Marvell specification v1.3 and v2.0)

The delay problem

RGMII requires the clock to arrive 1.5–2.0 ns after the data edges at the receiver (setup/hold window). Three ways to get it:

Adding the delay twice (PCB and PHY) or not at all produces the signature RGMII fault: link up at 1G with CRC errors or no traffic, while 100M works (100M has a 40 ns period and tolerates the skew). Fix by changing the PHY's delay register or the phy-mode.

In-band status

When idle, the PHY drives link, speed and duplex on RXD[3:0] so the MAC can reconfigure its clock divider without an MDIO read: RXD[0] link, RXD[2:1] speed (00 = 10, 01 = 100, 10 = 1000), RXD[3] duplex. Some MACs ignore it and rely on MDIO polling; mismatched expectations give a link that is up on the PHY and down on the MAC.

TBI and RTBI

Ten-Bit Interface: the 8b/10b-coded 1000BASE-X symbols (10 bits at 125 MHz, RTBI at DDR with 5 bits) between a MAC/PCS and an external SerDes or optical PHY. Obsolete on boards; its serial descendant is 1000BASE-X/SGMII (SGMII & serial gigabit).

Comparison

PHY management: MDIO/MDC

Contrast with pluggable modules, which are managed over I²C, not MDIO (Two-wire interface). A copper SFP's internal PHY is the exception: its MDIO registers are reachable through the module's I²C at a secondary address on many designs, which is how vendors set 10/100 fallback and auto-negotiation behaviour.

Common PHYs and their interfaces

Faults by interface

In CodingBox

Nothing on this page runs through the module's EEPROM — except the copper SFP, whose internal PHY (typically an 88E1111-class part) sits behind the same I²C that CodingBox reads. When a copper module works at 1G but not at 10/100, the answer lies in that PHY's configuration and the host's SGMII/1000BASE-X mode, not in the A0h identity bytes (Copper Ethernet & DAC, SGMII & serial gigabit).